The present invention relates to semiconductor memory devices, and more particularly, sense amplifiers for memory devices.
As a power supply voltage of a semiconductor memory device is lowered, a conventional sense amplifier may not operate stably in such semiconductor memory devices operating at a lower power supply voltage such as 1V.
FIG. 1 schematically illustrates a conventional semiconductor memory device capable of inputting and outputting one bit of data at a time. Referring to FIG. 1, a conventional semiconductor memory device comprises a memory cell array 10 having flash memory cells MC, a row decoder 12, a pre-discharge circuit 14, a data input and output gate circuit 16, a column decoder 18 and a sense amplifier 20. The operation of each block of the semiconductor memory device shown in FIG. 1 is described below.
The memory cell array 10 comprises flash memory cells MC connected between corresponding word lines WL1, WL2, . . . , WLi and corresponding bit lines BL1, BL2, . . . , BLj. The memory cell array 10 stores data “1” in the flash memory cells MC in an erase operation, and stores data “0” in a program operation. The row decoder 12 decodes a row address RA and generates a selection signal for selecting one of the word lines WL1, WL2, . . . , WLi.
The pre-discharge circuit 14 is connected between the respective bit lines BL1, BL2, . . . , BLj and a ground voltage, and comprises NMOS transistors N1 with respective gates to which a pre-discharge control signal DISCH is applied. The pre-discharge circuit 14 pre-discharges the bit lines BL1, BL2, . . . , BLj to a ground voltage in response to the pre-discharge control signal DISCH.
The data input and output gate circuit 16 is connected between the respective bit lines BL1, BL2, . . . , BLj and a data line, shown here as a common node COM, and comprises NMOS transistors N2 with respective gates to which corresponding column selection signals Y1, Y2, . . . , Yj are applied. The NMOS transistors N2 are turned on in response to the corresponding column selection signals Y1, Y2, . . . , Yj and transmit data between the corresponding bit lines BL1, BL2, . . . , BLj and the common node COM. The column decoder 18 decodes a column address CA and generates the corresponding respective column selection signals Y1, Y2, . . . , Yj. The sense amplifier 20 detects a current change of the common node COM in response to a bias control signal BIAS in a read operation, and generates a sense output signal Sout.
FIG. 2 illustrates a detailed circuit diagram of the sense amplifier shown in FIG. 1. Referring to FIG. 2, a sense amplifier in accordance with the conventional art comprises a PMOS transistor P1 and an NMOS transistor N3. The PMOS transistor P1 comprises a source to which a power supply voltage VDD is applied and gate and drain terminals connected to a sense output signal Sout generating terminal. The NMOS transistor N3 comprises a drain connected to the sense output signal Sout generating terminal, a gate to which the bias control signal BIAS is applied and a source connected to the common node COM.
In FIG. 2, the NMOS transistor N3 is larger than the PMOS transistor P1 in transconductance. Voltage gain of the sense amplifier is the transconductance ratio of the PMOS transistor P1 and the NMOS transistor N3. The operation of the circuit shown in FIG. 2 is described below.
During the pre-discharge operation, if the pre-discharge control signal DISCH having a power supply voltage is generated, NMOS transistors N2 are turned on in response to the pre-discharge control signal DISCH and the bit lines BL1, BL2, . . . , BLj become a ground voltage. At this time, because the bias control signal BIAS is at the ground voltage, the NMOS transistor N3 is turned off and the sense output signal Sout has a voltage, VDD−Vtp, wherein the Vtp refers a threshold voltage of the PMOS transistor P1.
When a read command is applied, the bias control signal BIAS is driven to the power supply voltage and the pre-discharge control signal DISCH transitions to a ground voltage level. Accordingly, the NMOS transistors N2 are turned off and the NMOS transistor N3 is turned on. Thus, a current flows through the NMOS transistor N3 and a voltage level of the common node COM increases. As the voltage of the common node COM increases, if a voltage difference between the gate and source of the NMOS transistor N3 is less than a threshold voltage of the NMOS transistor N3, the NMOS transistor N3 is turned off, which causes the voltage level of the common node COM to approach the bias voltage.
Upon the occurrence of such a condition, if the word line WL1 selection signal and the column selection signal Y1 are at the power supply voltage, the flash memory cell MC connected between the word line WL1 and the bit line BL1 is selected. If the flash memory cell MC stores a data “0”, the NMOS transistor N1 and the flash memory cell MC are turned on and a current flows from the common node COM to the flash memory cell MC, which lowers the voltage level of the common node COM and turns on the NMOS transistor N3. As a result, current flows through the NMOS transistor N3 and the voltage level of the sense output signal Sout generating terminal decreases. The voltage of the sense output signal Sout decreases by an amount of the voltage gain of the sense amplifier 20 times the reduced voltage of the common node COM.
If the selected flash memory cell MC stores a data “1”, the flash memory cell is turned off and current does not flow from the common node COM through the flash memory cell MC. Accordingly, the NMOS transistor N4 is turned off and the sense output signal Sout remains at a voltage level of VDD−Vtp.
The minimum power supply voltage for operation of the sense amplifier shown in FIG. 2 may be determined as follows. During a read operation, a minimum voltage of the data line is 0.4V and a minimum voltage difference between the drain and source of the NMOS transistor N3 is 0.2V, a threshold voltage of the PMOS transistor P1 is 0.4V, and an effective driving voltage of the PMOS transistor P1 is 0.2V, when the flash memory cell MC stores data “0”. Accordingly, the minimum operating power supply voltage of the sense amplifier 20 is obtained by adding the above voltage values, which equals around 1.2V.
That is, the conventional sense amplifier shown in FIG. 2 operates normally as long as no less than 1.2V of the power supply voltage is applied thereto. However, because a voltage drop of 0.4V occurs due to the PMOS transistor P1 acting as a diode, a power supply voltage of less than 1.2V may cause the sense amplifier to malfunction. However, considering process parameter variations in fabricating the semiconductor memory device with the sense amplifier and variation in operating conditions, such as a temperature, the minimum power supply voltage at which the sense amplifier operates normally and stably typically is far greater than 1.2V. In conclusion, the conventional sense amplifier shown in FIG. 2 may not operate normally and stably at a low power supply voltage, such as 1.0V or less.